Comparator circuits are used in electronic circuits e.g. to compare a first and a second voltage to determine which one of the first and the second voltage is the largest. For example, in an analog-to-digital converter (ADC), one or more comparator circuits may be used to compare an analog input voltage, or a voltage derived therefrom, with one or more reference-voltage levels in order to generate a digital output value corresponding to the analog input voltage.
Offset-errors are present in comparator circuits, e.g. due to mismatch between components, such as transistors, in the comparator circuits. A process known as auto zeroing may be used to compensate for the offset-errors. For example, a first switch (e.g. MOS transistor) may be connected between the positive input terminal and the negative output terminal of a fully differential comparator circuit. In addition, a second switch may be connected between the negative input terminal and the positive output terminal of the comparator circuit. The first and second switches are closed during an auto-zero phase to compensate for the offset error by providing a negative feedback loop. To obtain high gain, two or more comparator circuits may be connected in cascade in a comparator arrangement, where the output terminals of a comparator circuit are operatively connected to the input terminals of a succeeding comparator circuit via capacitors. Such a comparator arrangement is e.g. disclosed in the background section of U.S. Pat. No. 4,962,323.
In order to obtain relatively efficient and fast offset-error compensation with the arrangement describe above, it is required that the on resistances of the first and the second switch are relatively low. Therefore, the switches need to be implemented with relatively wide transistors. As a consequence, the first and the second switch provide a relatively high parasitic capacitive load to the comparator circuit, which may limit the bandwidth of the comparator circuit. In addition, the capacitors connected between comparator circuits may also be a limiting factor for the bandwidth. In an ADC, such a bandwidth limitation in a comparator circuit may limit the maximum sampling frequency of the ADC.
Hence there is a need for an offset-error compensated comparator circuit with improved bandwidth.